When starting operation of the FPGA circuit, a configuration is performed to set configuration data (or FPGA circuit data) using a configuration circuit illustrated in FIG. 1 or FIG. 2, for example. FIG. 1 is a diagram for explaining an example of the configuration circuit with respect to a single FPGA circuit, and FIG. 2 is a diagram for explaining an example of the configuration circuit with respect to a plurality of FPGA circuits.
In FIG. 1, a FPGA circuit (or ROM (Read Only Memory) circuit) 1-1 is formed by a flash memory that stores configuration data “DATA” of a FPGA circuit 2 specified by a user. The configuration data “DATA” include parameters, such as a clock frequency (or operation frequency), and circuit data of the FPGA circuit 2.
On the other hand, the FPGA circuit 2 includes a configuration data memory 21, a FPGA internal circuit 22, an input and output (I/O) buffer 23, a configuration control circuit 24, a clock generating circuit 25, and an I/O buffer 26 that are connected as illustrated in FIG. 1. The configuration control circuit 24 includes a CRC (Cyclic Redundancy Check) circuit 241, a main controller 242, and a decoder 243. The clock generating circuit 25 is formed by a ring oscillator that includes a tap adjusting circuit 251 and a plurality of inverter circuits 252 that are connected in series. The clock generating circuit 25 generates a configuration clock signal CLK to be output from the FPGA circuit 2.
The memory 21 stores set values that determine the logic of the FPGA internal circuit 22, and the set values determine various settings of resources within the FPGA circuit 2. The FPGA internal circuit 22 forms a logic function part in which the set values stored in the memory 21 are set. The I/O buffer 23 forms an interface usable by a user circuit (not illustrated). In the configuration control circuit 24, the CRC circuit 241 detects a data error by comparing a CRC code added to the configuration data “DATA” and a CRC code generated from the configuration data “DATA” read from the configuration circuit 1-1 and input to the FPGA circuit 2, and supplies to the main controller 242 an error detection signal that indicates whether the data error was detected. The main controller 242 supplies the clock frequency within the configuration data “DATA” depending on whether the error detection signal indicates that the data error was detected. In addition, when no data error is detected and the configuration is successful, the main controller 242 outputs a success signal that indicates that the configuration was successful. On the other hand, when the data error is detected and the configuration fails, the main controller 242 outputs an error signal that indicates that a configuration occurred. The decoder 243 decodes the value of the clock frequency, and controls the tap adjusting circuit 251 of the clock generating circuit 25 based on the decoded value, in order to adjust the tap of the inverter circuits 252 and set the frequency of the clock signal CLK generated from the clock generating circuit 25. The clock signal CLK is supplied to the configuration control circuit 24, and is also supplied to the configuration circuit 1-1 via the I/O buffer 26.
In FIG. 2, a configuration circuit 1-1 is provided with respect to a plurality of FPGA circuits (#1 through #N, where N is a natural number greater than 1) 2-1 through 2-N. In this example, the FPGA circuit 2-1 functions as a master, and the FPGA circuits 2-2 through 2-N function as slaves. The configuration circuit 1-2 inputs the configuration data “DATA” to the master FPGA circuit 2-1, in a manner similar to the configuration circuit 1-1 described above. The master FPGA circuit 2-1 supplies the clock signal CLK to the configuration circuit 1-2, in a manner similar to the FPGA circuit 2 described above. On the other hand, the clock signal CLK is also supplied to the slave FPGA circuits 2-2 through 2-N. In addition, the configuration data “DATA” from the configuration circuit 1-2 are successively supplied to the slave FPGA circuits 2-2 through 2-N via the master FPGA circuit 2-1.
For the sake of convenience, a description will be given of the configuration for the case illustrated in FIG. 1.
The configuration of the FPGA circuit 2 using the configuration circuit 1-1 illustrated in FIG. 1 may fail. The main reason for the failure of the configuration is in most cases a transfer failure or error of the configuration data “DATA”, caused by mixing of noise to the configuration data “DATA” and signal decay or deterioration on a printed circuit board (not illustrated) mounted with the FPGA circuit 2. When the configuration of the FPGA circuit 2 fails, the configuration is in most cases ended as a configuration error. When making a reconfiguration of the FPGA circuit 2, the configuration is re-executed under the same conditions as the failed configuration.
Conventionally, the configuration of the FPGA circuit 2 is performed by providing a frequency setting path from the configuration circuit 1-1 to the clock generating circuit 25 within the FPGA circuit 2, and manually adjusting the value of the clock frequency of the configuration circuit 1-1 in order to manually adjust the set value of the clock frequency of the FPGA circuit 2 by the user. This manual adjustment is repeated until the configuration of the FPGA circuit 2 becomes a success, thereby requiring a relatively large number of steps. In the configuration circuit 1-1 illustrated in FIG. 1, the manual adjustment of the clock frequency is possible, but the manual adjustment of the slew rate is not possible.
For example, it is conceivable to avoid the configuration error by setting the clock frequency to an extremely low frequency, so that the configuration of the FPGA circuit 2 becomes a success. However, this conceivable method should not be employed for the following reasons.
That is, due to the increase in the scale of the recent FPGA circuit, the tendency is for the amount of configuration data to increase and for the time required for the configuration to increase. The starting of a system that includes the FPGA circuit is affected by the time required for the configuration. For this reason, the clock frequency of the configuration of the FPGA circuit is desirably set to a relatively high frequency in order to reduce the configuration time. However, when the clock frequency is set to the relatively high frequency, the slew rate of the clock signal becomes relatively high, and it becomes necessary to make a rising edge of the signal sharp.
On the other hand, if a device defect exists within the FPGA circuit, layout and wiring information that does not use the defective device may be found by switching a plurality of layout and wiring information prepared in advance, as proposed in a Japanese Laid-Open Patent Publication No. 2005-243937, for example. However, this proposed method does not take into consideration the error in the configuration itself of the FPGA circuit.
A self-configuration function of a programmable device is proposed in a Japanese Laid-Open Patent Publication No. 2000-101421, for example.
Hence, in the configuration of the FPGA circuit using the conventional manual adjustment, a considerable burden is put on the user every time the adjustment of the clock frequency is unsatisfactory, because the clock frequency of the FPGA circuit is manually adjusted to suit an operating environment in which the FPGA circuit is used, such as the circuit board on which the FPGA circuit is mounted and the ambient temperature of the FPGA circuit. In other words, the user must repeat the manual adjustment in order to optimize the clock frequency. In addition, even if the configuration circuit is the same, there are cases where it may be better to change the clock frequency for each FPGA circuit product, and in such cases, the cost of manually adjusting the clock frequency is generated for each product. Hence, it may be difficult to reduce the cost of manually adjusting the clock frequency when performing the configuration of the FPGA circuit.
Furthermore, the plurality of FPGA circuits 2-1 through 2-N may be connected as illustrated in FIG. 2, and the configuration may fail due to the effects of unpredictable reflection noise or the like, depending on the interconnection or wiring on the circuit board mounted with the FPGA circuits 2-1 through 2-N.
Therefore, the conventional configuration of the FPGA circuit requires the manual adjustment of the clock frequency of the FPGA circuit, and there was a problem in that the burden on the use to make the manual adjustment is relatively large.